Title: NaPer: A TSV Noise-Aware Placer
Authors: Lee, Yu-Min
Pan, Kuan-Te
Chen, Chun
電機工程學系
Department of Electrical and Computer Engineering
Keywords: Coupling aware;layout;physical design;placement;three-dimensional integrated circuits;through-silicon via (TSV) coupling
Issue Date: 1-May-2017
Abstract: Through-silicon-via (TSV)-to-TSV coupling issue can degrade the signal integrity in 3-D integrated circuit designs. This paper develops a 3-D partitioning-based force-directed placer, NaPer, to reduce the total coupling noise between TSVs and alleviate the maximum coupling noise between them. We introduce two denoise forces: TSV decoupling force and TSV density force. The TSV decoupling force is determined by the coupling noise between TSVs for separating strong coupling TSVs, and the TSV density force is determined by the TSV density for evenly distributing TSVs. The experimental results show that NaPer can effectively reduce 15.0% total TSV coupling noise and 42.7% maximum TSV coupling noise on average with only 4.5% wirelength overhead. Besides, NaPer also shows great performance in wirelength that is competitive to the state-of-the-art 3-D placer.
URI: http://dx.doi.org/10.1109/TVLSI.2016.2645230
http://hdl.handle.net/11536/145455
ISSN: 1063-8210
DOI: 10.1109/TVLSI.2016.2645230
Journal: IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS
Volume: 25
Begin Page: 1703
End Page: 1713
Appears in Collections:Articles