Title: | Timing Macro Modeling for Efficient Hierarchical Timing Analysis |
Authors: | Jiang, Iris Hui-Ru Lee, Pei-Yu 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
Keywords: | Static timing analysis;hierarchical timing analysis;timing macro modeling;interface logic model;extracted timing model |
Issue Date: | 1-Jan-2018 |
Abstract: | As designs continue to grow in size and complexity, EDA paradigm shifts from flat to hierarchical timing analysis. In this paper, we discuss timing macro modeling, which is the key to enable efficient and accurate hierarchical timing analysis. We briefly review conventional models and recent research progresses in timing macro modeling. We try to answer the following questions: How can timing macro models be made compact and accurate? How do state-of-the art works maintain model accuracy, model size, model generation performance, and model usage performance? Finally, future research directions on timing macro modeling are identified. |
URI: | http://dx.doi.org/10.1109/ISVLSI.2018.00134 http://hdl.handle.net/11536/150728 |
ISSN: | 2159-3469 |
DOI: | 10.1109/ISVLSI.2018.00134 |
Journal: | 2018 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI (ISVLSI) |
Begin Page: | 714 |
End Page: | 714 |
Appears in Collections: | Conferences Paper |