Title: Estimating likelihood of correctness for error candidates to assist debugging faulty HDL designs
Authors: Jiang, TY
Liu, CNJ
Jou, JY
電子工程學系及電子研究所
Department of Electronics Engineering and Institute of Electronics
Issue Date: 2005
Abstract: Debugging priority is a helpful technique to assist debugging faulty HDL designs [9]. However, debugging priority obtained by sorting confidence score is not good enough due to the inaccuracy in estimating likelihood of correctness for error candidates. Therefore, we developed Refined Confidence Score for deriving better debugging priority.
URI: http://hdl.handle.net/11536/17798
ISBN: 0-7803-8834-8
ISSN: 0271-4302
Journal: 2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS
Begin Page: 5682
End Page: 5685
Appears in Collections:Conferences Paper