Title: | A new BIST scheme based on a summing-into-timing-signal principle with self calibration for the DAC |
Authors: | Chen, GX Lee, CL Chen, JE 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
Issue Date: | 2004 |
Abstract: | In this paper, we propose a new BIST scheme for the Digital-to-Analog Converter (DAC). For the scheme, an analog summer is employed and the tested signal is transformed into a timing signal for a more precise measurement. Also, a calibration circuit is added to calibrate analog imperfection to increase accuracy of the BIST circuit. A 8-bit DAC BIST circuit is designed for demonstration. |
URI: | http://hdl.handle.net/11536/18181 |
ISBN: | 0-7695-2235-1 |
ISSN: | 1081-7735 |
Journal: | 13TH ASIAN TEST SYMPOSIUM, PROCEEDINGS |
Begin Page: | 58 |
End Page: | 61 |
Appears in Collections: | Conferences Paper |