| Title: | ESD implantations in 0.18-mu m salicided CMOS technology for on-chip ESD protection with layout consideration |
| Authors: | Ker, MD Chuang, CH 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| Issue Date: | 2001 |
| URI: | http://hdl.handle.net/11536/19014 |
| ISBN: | 0-7803-6675-1 |
| Journal: | PROCEEDINGS OF THE 2001 8TH INTERNATIONAL SYMPOSIUM ON THE PHYSICAL & FAILURE ANALYSIS OF INTEGRATED CIRCUITS |
| Begin Page: | 85 |
| End Page: | 90 |
| Appears in Collections: | Conferences Paper |
- ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technology / Ker, MD;Chuang, CH;Lo, WY
- Substrate-triggered ESD protection circuit without extra process modification / Ker, MD;Chen, TY
- ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness / Ker, MD;Hsu, HC;Peng, JJ
- Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process / Ker, MD;Chen, TY
- Layout design on multi-finger MOSFET for on-chip ESD protection circuits in a 0.18-mu m salicided CMOS process / Ker, MD;Chuang, CH;Lo, WY
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