A new hardware design and FPGA implementation for Internet routing towards IP over WDM and terabit routers

Abstract

With the advent of world wide web and the services on it, there is a strong demand for the nodes that make internet routing with guaranteed speed and throughput. Current 40-channel WDM (Wavelength Division Muitiplexing) has boosted a single 2.5Gbps OC-48 link to 100Gbps, so the requirement to make IPv4 (Internet Protocol version 4) routing table lookup is 100MLPS (million lookups per second). The emerging 96-channel WDM and 10Gbps OC-192 fibers certainly demand much more. Previous works on East IPv4 routing table lookup used indirect RAM indexing or CPU caching or CAM (Content Addressable Memory) to achieve a few or tens MLPS. Their theoretical best performances depend on the memory access speed and some of them are not extensible to accommodate the forthcoming IPv6. In this paper we describe a novel way to do this work with only a FPGA. And this approach, which utilize the logic modeling and minimization techniques, promises a capability to make IPv4 (and IPv6) routing decisions in a pipelined fashion within only a FPGA CLB delay time.