A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMS

Title:	A new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMS
Authors:	Wu, CY Yu-Yee, L 電子物理學系電子工程學系及電子研究所 Department of Electrophysics Department of Electronics Engineering and Institute of Electronics
Issue Date:	1999
Abstract:	A novel 1.5-bit (3-level)/cell storage technique is described. This sense amplifier of DRAM can sense the ternary state. Thus, this structure can effectively reduce the bit-cost. The proposed DRAM can be operated at 1.5V without changing the common DRAM process.
URI:	http://hdl.handle.net/11536/19416
ISBN:	0-7803-5471-0
Journal:	ISCAS '99: PROCEEDINGS OF THE 1999 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 1: VLSI
Begin Page:	47
End Page:	50
Appears in Collections:	Conferences Paper

APA	Wu, C., & Yu-Yee, L. (1999). new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMS. WOS:000081715100012.
Bibtex	@article{Wu1999new, title={new dynamic ternary sense amplifier for 1.5-bit/cell multi-level low-voltage CMOS DRAMS}, author={Wu, CY and Yu-Yee, L}, journal={WOS:000081715100012}, year={1999}, url={https://ir.lib.nycu.edu.tw/handle/11536/19416}, }