| Title: | Scalable VLSI architectures for full-search block matching algorithms |
| Authors: | Yeh, YH Lee, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| Issue Date: | 1996 |
| URI: | http://hdl.handle.net/11536/19796 |
| ISBN: | 0-7803-3259-8 |
| Journal: | INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, PROCEEDINGS - VOL II |
| Begin Page: | 1035 |
| End Page: | 1038 |
| Appears in Collections: | Conferences Paper |
- 應用階層式方塊比對演算法之動態影像預估處理器設計 / 范凱婷;Fan, Kai-Ting;李鎮宜;Lee Chen-Yi
- 完全搜尋區塊比對演算法之 VLSI 陣列設計 / 高治平;Chih-Pring Gau;劉啟民;Chi-Min Liu
- On the data reuse and memory bandwidth analysis for full-search block-matching VLSI architecture / Tuan, JC;Chang, TS;Jen, CW
- Cost-effective VLSI architectures and buffer size optimization for full-search block matching algorithms / Yeh, YH;Lee, CY
- An efficient VLSI architecture for full-search block matching algorithms / Lee, CY;Lu, MC
- An efficient hierarchical motion estimation on algorithm and its VLSI architecture / Wu, BF;Peng, HY;Chen, CJ;Yu, TL
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