| Title: | The CMOS design of robust neural chip with the on-chip learning capability |
| Authors: | Wu, CY Liu, RY Jou, IC ShyhJYE, FJ 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| Issue Date: | 1996 |
| URI: | http://hdl.handle.net/11536/19804 |
| ISBN: | 0-7803-3073-0 |
| Journal: | ISCAS 96: 1996 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, VOL 3 |
| Begin Page: | 426 |
| End Page: | 429 |
| Appears in Collections: | Conferences Paper |
- The multi-chip design of analog CMOS expandable modified Hamming neural network with on-chip learning and storage for pattern classification / Lan, JF;Wu, CY
- 高性能互補式金氧半影像感測器、矽視網膜及具學習能力之影像處理類神經網路晶片系統設計研究(I) / 吳重雨;CHUNG-YUWU
- 高性能互補式金氧半影像感測器、矽視網膜及具學習能力之影像處理類神經網路晶片系統設計研究(II) / 吳重雨;CHUNG-YUWU
- 高性能互補式金氧半影像感測器、矽視網膜及具學習能力之影像處理類神經網路晶片系統設計研究(III) / 吳重雨;CHUNG-YUWU
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