On designing of 4-valued memory with double-gate TFT

Title:	On designing of 4-valued memory with double-gate TFT
Authors:	Lee, CL Chern, HN Liao, MS Wang, HM 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
Keywords:	multi-valued logic;double-gate thin film transistor;SRAM;circuit design
Issue Date:	1995
URI:	http://hdl.handle.net/11536/20013
ISBN:	0-7803-2764-0
ISSN:	0195-623X
Journal:	1995 25TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS
Begin Page:	187
End Page:	192
Appears in Collections:	Conferences Paper