Title: | A SILICIDATION-INDUCED PROCESS CONSIDERATION FOR FORMING SCALE-DOWN SILICIDED JUNCTION |
Authors: | CHENG, HC JUANG, MH LIN, CT HUANG, LM 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
Issue Date: | 1-Sep-1994 |
Abstract: | A process consideration for forming silicided shallow junctions, arising from silicidation process, has been discussed. The CoSi2 shallow p+n junctions formed by various schemes are characterized. The scheme that implants BF2+ ions into thin Co films on Si substrates and subsequent silicidation yields good junctions, but the problems about the dopant drive-in and knock-on of metal deeply degrade this scheme. In the regime that implants the dopant into Si and then Co deposition, however, a large perimeter leakage of 0.1 nA/cm is caused. Generation current, associated with a defect-enhanced diffusion of Co in Si during silicidation, dominates the leakage. A high-temperature pre-activation prior to Co deposition reduces the perimeter leakage to 0.038 nA/cm, but which deepens the junctions. |
URI: | http://dx.doi.org/10.1109/55.311128 http://hdl.handle.net/11536/2340 |
ISSN: | 0741-3106 |
DOI: | 10.1109/55.311128 |
Journal: | IEEE ELECTRON DEVICE LETTERS |
Volume: | 15 |
Issue: | 9 |
Begin Page: | 342 |
End Page: | 344 |
Appears in Collections: | Articles |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.