A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator

Title:	A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator
Authors:	Wu, CY Chou, CY 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
Keywords:	CMOS technology;double-quadrature architecture;IEEE 802.11a;low-noise amplifier;quadrature generator;quadrature voltage-controlled oscillator;radio frequency;receiver
Issue Date:	1-Mar-2004
Abstract:	A 5-GHz CMOS double-quadrature front-end receiver for wireless LAN application is proposed. In the receiver, a one-stage RLC phase shifter is used to generate quadrature RF signals. Implemented in 0.18 mum CMOS technology, the receiver chip can achieve 50.6-dB image rejection with power dissipation of 22.4 mW at 1.8-V voltage supply.
URI:	http://dx.doi.org/10.1109/JSSC.2003.822779 http://hdl.handle.net/11536/26982
ISSN:	0018-9200
DOI:	10.1109/JSSC.2003.822779
Journal:	IEEE JOURNAL OF SOLID-STATE CIRCUITS
Volume:	39
Issue:	3
Begin Page:	519
End Page:	521
Appears in Collections:	Articles

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