Title: | Ultra-shallow junction formation using implantation through capping nitride layer on source/drain extension |
Authors: | Hsien, LJ Chan, YL Chao, TS Jiang, YL Kung, CY 電子物理學系 Department of Electrophysics |
Keywords: | shallow junction;nitride;CMOS |
Issue Date: | 1-Jul-2002 |
Abstract: | Method for forming ultra-shallow p(+)/n is demonstrated for 0.15 mum p-type metal-oxide-semiconductor field-effect transistor (pMOSFET). The approach includes a capping ultra-thin nitride on the source/drain extension regions followed by a low energy source/drain (S/D) extension implantation. Ultra shallow p(+)/n junctions can be obtained with depth of 27 nm and sheet resistivity of 1007 Omega/square. |
URI: | http://dx.doi.org/10.1143/JJAP.41.4519 http://hdl.handle.net/11536/28705 |
ISSN: | 0021-4922 |
DOI: | 10.1143/JJAP.41.4519 |
Journal: | JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS |
Volume: | 41 |
Issue: | 7A |
Begin Page: | 4519 |
End Page: | 4520 |
Appears in Collections: | Articles |
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