應用改良式無負載架構之8位元100百萬赫茲取樣互補式金氧半導管式類比數位轉換器

Abstract

有著高速、中解析度及低功率的特性，導管式類比數位轉換器被廣泛使用於通訊及影像訊號處理等商業應用。於此篇論文中，一個嶄新的改良式無負載架構被提出。此架構可增加導管式類比數位轉換器中倍乘式數位類比轉換器的頻寬，進而提升轉換速率。此外，藉由在鄰近兩級間使用運算放大器共用技術，功率消耗及晶片面積也可被有效降低。應用上述兩種技術，數位類比轉換器可達到較高轉換速率且消耗較低功率。 在此篇論文中，兩個導管式數位類比轉換器被設計於台積電0.18微米互補式金氧半製程。第一個設計是一個應用運算放大器共用技術10位元每秒100百萬取樣導管式數位類比轉換器，第二個設計是一個應用改良式無負載架構及運算放大器共用技術之8位元每秒100百萬取樣導管式數位類比轉換器。採用每級1.5位元的架構以獲得較高的操作速度，所以此類比數位轉換器主要包含一個前端取樣保持電路、八個(或六個)串接1.5位元單級和最後一級的2位元快閃式轉換器。所有類比電路皆以全差動架構設計，而在1.8伏特供應電壓下擁有峰對峰值1.6伏特的輸入擺幅。在每秒100百萬取樣及5百萬赫茲輸入訊號下，第一個設計可達到59.95dB 訊號對雜訊及失真比 (SNDR), 71.18dB 無寄生動態範圍 (SFDR)及9.67有效位元(ENOB)。 最大差動非線性誤差 (DNL)為0.4LSB而最大積分非線性誤差 (INL)為1.07LSB。在每秒100百萬的取樣速度下功率消耗為72.6毫瓦而晶片面積為1.95毫米平方。而在每秒100百萬取樣及10百萬輸入訊號下，第二個設計可達到46.98dB 訊號對雜訊及失真比 (SNDR), 57.24dB 無寄生動態範圍 (SFDR)及7.51有效位元(ENOB)。 最大差動非線性誤差 (DNL)為0.38LSB而最大積分非線性誤差 (INL)為0.88LSB。在每秒100百萬的取樣速度下功率消耗為78毫瓦而晶片面積為1.89毫米平方。

With high-speed, medium-resolution, and low-power characteristics, pipelined analog-to-digital converters (ADCs) are very popular for a wide variety of commercial applications, including data communications and image signal processing. In this thesis, a newly improved loading-free architecture is proposed. It much enhances the bandwidth of the multiplying digital-to-analog converter (MDAC) circuit in pipelined ADC, and thus the conversion rate can be speeded up. Besides, the power consumption and chip area can also be reduced efficiently by using the opamp-sharing technique between two successive stages. With above two techniques, the ADC can achieve much higher conversion rate and consume less power. In this thesis, there are two pipelined ADCs implemented in TSMC 0.18-μm CMOS process. The first design is a 10-bit 100MS/s pipelined ADC with opamp-sharing technique, and the second design is an 8-bit 100-MS/s pipelined ADC with both improved loading-free architecture and opamp-sharing technique. To achieve higher operation speed, the 1.5-bit/stage architecture is adopted, and thus these ADCs mainly consist of one front-end S/H, eight (or six) cascaded 1.5-bit stages, and a 2-bit flash ADC in the last stage. All analog circuits are fully differential with a 1.6Vpp input signal swing at 1.8-V supply voltage. The first design achieves 59.95dB SNDR, 71.18dB SFDR, 9.67bit ENOB for a 5-MHz input signal at 100-MS/s. The maximum DNL is 0.4LSB and the maximum INL is 1.07LSB. The power consumption at 100MS/s sampling rate is 72.6 mW and the chip size is 1.95mm2. The second design achieves 46.98dB SNDR, 57.24dB SFDR, 7.51bit ENOB for a 10-MHz input signal at 100-MS/s. The maximum DNL is 0.38LSB and the maximum INL is 0.88LSB. The power consumption at 100MS/s sampling rate is 78 mW and the chip size is 1.89mm2.