限制理論應用於晶圓廠黃光區有機台群組限制的投料及派工模式

Abstract

半導體晶圓製造近年來隨著技術的演進，元件的大小從微米漸漸走向奈米的尺度，因此從晶圓直徑的不斷增加、更加精密的微影技術、以及晶圓廠投資成本的上揚等，都是必須面對的挑戰。這時在半導體製程中最舉足輕重的步驟-微影(Lithography)就相當重要，隨著製程微小化的趨勢，為降低不同的微影步進機台對製程所產生的變異，而產生對微影製程所使用的機台有所謂的微影機台群組限制的要求。也就是當產品於第一關鍵黃光層若使用某一微影對準機台，為使以後的其他關鍵層別也能互相對準，因此要求後續的各關鍵層別亦限定使用同一機台。微影機台群組限制雖可增加製程的穩定性，但同時也使得瓶頸機台的管理益加困難。

本研究使用限制理論的方法並以實際某一晶圓廠為例，透過限制驅導式的管理對投料的時機及數量做控制，以達到所有關鍵層別內的瓶頸微影機台的負荷平衡，避免造成個別機台負荷過高或機台閒置的現象；在派工上，則以限制理論非瓶頸資源全力支援瓶頸資源的觀念，對介於關鍵層別內的非瓶頸機台的派工，以滿足其所限定的微影機台的標準負荷為目標，當其負荷相對過低時，則對其上游所限定的微影機台的晶圓批提高其派工等級；透過以上的投料、派工方法以達到產出最大，縮短生產週期時間，及準時達交的目標。

本研究經實際晶圓廠的驗證可知，應用限制理論於瓶頸機台的投料法則及非瓶頸機台的派工法則，確實能達到產出最大、縮短生產週期時間、提高產品準時達交的目標。

From micron to nanometer technology in semiconductor manufacturing, increasing investment capital and more precise lithography in high-density device is the tendency and challenge to IC (Integrated Circuit) function enhancement and cost reduction. Obviously, photolithography becomes more and more critical process. In this technology trend, to reduce the impact of precise lithography process constraint for stable process level between different Stepper machines, we must follow the Stepper Group Limit rule, it means that if one lot uses the stepper machine X to process in the first critical photo layer will have to use the same stepper machine X to process the following other critical photo layers. This limitation can guarantee the process stability, but it makes more difficult and less flexibility for production control especially the stepper is always the bottleneck in FAB. This research applies TOC concept in developing a releasing and dispatching model to balance the capacity loading under stepper group limitation. The wafer is released to adjust dynamically the actual loading between stepper group limit machines and to avoid more WIP concentrated on one machine and the other machine with high idle rate by low WIP. In dispatching, we also follow the non-bottleneck fully support the bottleneck requirement as TOC concept and develop a model to dynamically upgrade the lot priority . The results after implementing in a FAB shows that the developed model does reduce the cycle time, increase on-time delivery and improve the bottleneck utilization.