應用於地面及手持數位電視廣播與室內無線接收機之同步設計

Abstract

在此篇論文中，提出應用於手持及地面數位電視廣播與室內無線60GHz規格之同步設計。本論文探索基頻數位信號處理演算法和架構，以達成所要求之系統規格。此外，整合與實現低功率及有效率的資料路徑，以驗證所提出之基頻設計。為了完成同步設計，本論文採用並修改數個廣泛使用的資料路徑，像是移動總合架構、單埠記憶體式延遲線、差值編碼、迴路濾波器、複數乘法器、座標旋轉數位運算演算法與直流錯誤移除方法來有效率地實現同步之硬體。

提出之手持及地面數位電視廣播基頻接收機包含，模式、符元及保護區間偵測、載波頻率與取樣時脈同步、快速兩階段之散佈領航碼同步與通道估測。保護區間偵測採用無除法之相關方法。載波同步與取樣時脈同步使用記憶體分享架構。快速兩階段之散佈領航碼同步方法加速領航碼位置之偵測。為了增加記憶體使用率，通道估測重新利用符元偵測之記憶體。此外，差值編碼減少記錄領航碼位置的儲存器之使用量。相位預測方法減少相位累加器之操作次數。系統模擬結果顯示此接收機可達位元錯誤率之要求。最後，此接收機之晶片使用0.18µm互補式金氧半導體技術製造和驗證，其核心面積為12.96 mm2。

對於應用於60GHz之室內無線規格，此篇論文提出用於正交分頻多工與單載波接收機之雙模架構。標頭與符元偵測、載波頻率與取樣時脈同步與部分的通道估測共用於正交分頻多工模式與單載波模式，以減少硬體複雜度。此外，提出一個應用於取樣頻率誤差補償器之平行化架構。此平行取樣頻率誤差補償器解決內插器之不規則存取並加速處理速度。合成結果顯示，在使用90nm互補式金氧半導體技術下，此架構可操作於400 MHz且在八倍平行化下可達到3.2Gs/s，而其等效邏輯閘數約為204K。

In this thesis, synchronization designs for DVB-T/H and indoor wireless 60GHz standards are present. Baseband digital signal processing algorithms and architectures are explored to achieve the required system specifications. Moreover, low power and area efficient data-paths are integrated and implemented to verify the proposed baseband designs. To accomplish synchronization designs, several widely used data-paths, such as the moving sum architecture, the single port based delay line, the differential encoding scheme, the loop filter, the complex multiplier, CORDIC algorithm and the removing DC error scheme are adopted and modified to implement the hardware of synchronizations efficiently.

The proposed DVB-T/H baseband receiver contains a mode/symbol/guard interval detection, a carrier frequency and sampling clock synchronization, a two-stages fast scattered pilot synchronization, and a channel estimation. The guard interval detection adopts a division free correlation method. The carrier synchronization and sampling clock synchronization uses a memory sharing architecture. A two-stages fast scatted pilot synchronization method increases the speed of the detection of pilot location. To increase memory utility, the channel estimation reuses the memory of the symbol detection. Besides, the differential encoding scheme reduces the storage requirement of recording pilot location. The phase predictive scheme reduces the operations of phase accumulators. The system simulation results show this receiver can achieve BER requirement. Finally, the chip of this receiver was fabricated and verified in a 0.18µm CMOS technology and its core size is 12.96 mm2.

For indoor wireless 60GHz standards, this thesis presents a dual mode architecture of the OFDM/single carrier mode receiver. The preamble/symbol detection, the carrier and sampling clock synchronization, and parts of channel estimation are shared in OFDM mode and SC mode to reduce hardware complexity. Besides, a parallel architecture for a sampling clock offset compensator is proposed. The parallel sampling clock offset compensator solves the irregular access form interpolators and increases the speed of processing. The synthesis result shows that it can operate at 400 MHz and achieve 3.2 Giga samples per second with a 8X parallelization with about 204 K equivalent gate counts by using 90nm CMOS process.