| Title: | EQUIVALENT-CIRCUIT MODEL IN GRAIN-BOUNDARY BARRIER LAYER CAPACITORS |
| Authors: | CHIOU, BS LIN, ST DUH, JG CHANG, PH 電控工程研究所 Institute of Electrical and Control Engineering |
| Issue Date: | 1-Oct-1989 |
| URI: | http://dx.doi.org/10.1111/j.1151-2916.1989.tb06008.x http://hdl.handle.net/11536/4284 |
| ISSN: | 0002-7820 |
| DOI: | 10.1111/j.1151-2916.1989.tb06008.x |
| Journal: | JOURNAL OF THE AMERICAN CERAMIC SOCIETY |
| Volume: | 72 |
| Issue: | 10 |
| Begin Page: | 1967 |
| End Page: | 1975 |
| Appears in Collections: | Articles |
- EPR EVIDENCE FOR COMPENSATING DEFECTS IN BATIO3 GRAIN-BOUNDARY BARRIER LAYER CAPACITORS / CHIOU, BS;LIN, ST;DUH, JG
- Effect of bottom electrodes on dielectric relaxation and defect analysis of (Ba0.47Sr0.53)TiO3 thin film capacitors / Tsai, MS;Tseng, TY
- Very high density RF MIM capacitor compatible with VLSI / Chiang, KC;Lai, CH;Chin, A;Kao, HL;McAlister, SP
- Dielectric relaxation and defect analysis of Ta2O5 thin films / Ezhilvalavan, S;Tsai, MS;Tseng, TY
- Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices / Hsiao, Yi-Hsuan;Lue, Hang-Ting;Chen, Wei-Chen;Chang, Kuo-Pin;Shih, Yen-Hao
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