| Title: | A NEW GENERAL-METHOD TO MODEL SIGNAL TIMING OF E D NMOS LOGIC |
| Authors: | WU, CY LIN, YT 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics |
| Issue Date: | 1-Oct-1989 |
| URI: | http://hdl.handle.net/11536/4292 |
| ISSN: | 0098-9886 |
| Journal: | INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS |
| Volume: | 17 |
| Issue: | 4 |
| Begin Page: | 447 |
| End Page: | 464 |
| Appears in Collections: | Articles |
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- A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications / Tseng, YK;Wu, CY
- 區別製程邊界來提高記憶體編譯器產生出來的靜態隨機記憶體良率 / 蕭家棋;Chia-Chi Hsiao;陳宏明;Hung-Ming Chen
- THE ANALYSIS AND DESIGN OF CMOS MULTIDRAIN LOGIC AND STACKED MULTIDRAIN LOGIC / WU, CY;WANG, JS;TSAI, MK
- Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology / Ker, MD;Hsu, HC;Peng, JJ
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