環繞式閘極多晶矽奈米線薄膜電晶體於非揮發性記憶體研究

Abstract

近年多重閘極結構被廣泛的研究，目的是為了增加閘極控制能力，解決電晶體微小化後的問題。本實驗室之前已經利用環繞式的閘極結構，成功地應用於多晶矽奈米線薄膜電晶體，利用其優越的閘極掌控能力，抑制短通道效應，成功的提升電晶體的轉換特性。而本研究建立於之前的基礎上，將環繞式閘極結構的多晶矽奈米線電晶體與非揮發性記憶體結合，除了利用環繞式閘極結構提昇電晶體轉換特性，同時也利用其包覆奈米線通道時產生的角落效應，增加非揮發性記憶體的寫入抹除速度，抑制閘極注入的效率，改善傳統平面薄膜電晶體應用於非揮發性記憶體難以寫入抹除的現象。 元件完成後，同時比較環繞式閘極結構與三閘極結構的元件轉換特性，發現環繞式閘極元件擁有較大的驅動電流、較低臨界擺幅、較高開關電流比與較低的汲極引發能位障下降。但由於環繞式閘極優越的閘極掌控能力，也同時擁有較大的閘極引發汲極漏電流。在記憶體元件特性上，環繞式閘極結構因為較多的角落效應，在記憶體寫入抹除特性上優越於三閘極結構。另外也量測此新穎元件的可靠度特性，發現其元件電荷儲存能力與元件耐久性都擁有優異的特性。

Recently, multiple gate structures has been widely studied to increase channel controlability and to overcome limitations in device scaling down. In past study, Gate-All-Around structure in TFT has been proposed to improve channel controllability, to suppress short channel effect (SCE), and to increase device performance due to corner effect. In this thesis, gate-all-around (GAA) poly-Si nanowire (NW) TFTs with SONOS-type memory was demonstrated. The GAA structure is being used to not only increase the device performance but also create corner effect around the nanowire channel. It raises the P/E speed of SONOS-type memory, restrains the gate injection efficiency, and improves the fact of “hard-to-erase” in planer devices as flash memory. After the device fabricated, a comparison of device performance with GAA structure to TriGate structure were presented. It shows that the GAA device has a high driving current, a steep Subthreshold Swing, an absence of DIBL, and a high on/off current ratio, but gate induce drain leakage was serious than the planer device. The memory program and erase efficiency in the GAA device is better than TriGate device due to the increase of corners number. Furthermore, the device endurance and data retention measurement have also been demonstrated.