| Title: | A NEW CRITERION FOR TRANSIENT LATCHUP ANALYSIS IN BULK CMOS |
| Authors: | YANG, YH WU, CY 交大名義發表 電控工程研究所 National Chiao Tung University Institute of Electrical and Control Engineering |
| Issue Date: | 1-Jul-1989 |
| URI: | http://dx.doi.org/10.1109/16.30939 http://hdl.handle.net/11536/4338 |
| ISSN: | 0018-9383 |
| DOI: | 10.1109/16.30939 |
| Journal: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
| Volume: | 36 |
| Issue: | 7 |
| Begin Page: | 1336 |
| End Page: | 1347 |
| Appears in Collections: | Articles |
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- TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERION / KER, MD;WU, CY
- Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology / Ker, MD;Lo, WY
- Failure analysis and solutions to overcome latchup failure event of a power controller IC in bulk CMOS technology / Chen, SH;Ker, MD
- 互補式金氧半暫態鎖住效應及晶片上靜電放電保護電路之研究. / 柯明道;Ming-Dou Ker;吳重雨;Chung-Yu Wu
- Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs / Hsu, Sheng-Fu;Ker, Ming-Dou
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