應用於超寬頻之電容回授匹配與電流再利用之低雜訊放大器

Abstract

本篇論文主要是探討超寬頻低雜訊放大器之設計與分析。在第一級部 分，為了達到寬頻的輸入匹配，我們採用電容回授的方式，分別對高頻及低頻作輸入匹配，及利用電感(LS)、電容(Cgd)回授來達成輸入匹配；接著第二級部分，利用疊接方式來達到電流重複使用，以降低功率消耗，為了達到寬頻的增益，使用並串連尖峰電感(shunt-series peaking)的頻寬延伸技術來完成寬頻增益的目的；最後我們採用一個LC串聯電路方式，來達到輸出匹配。電路採用 TSMC 0.18μm 1P6M CMOS 製程實現，在此架構電路實際量測結果如下：在供應電壓1.5V下，頻寬為3.1 ~ 10.6GHz，輸入反射係數小於-10.07以下，輸出反射係數小於-15.2 dB以下，平均順向增益大於6.66 dB，逆向隔離小於-28.25 dB以下，雜訊指數為3.13~7.05 dB，input P1dB為-16dBm，最小值為IIP3為-10dBm，晶片消耗功率為26.7mW.

This thesis discusses the design and analysis of an ultra wideband low-noise amplifier. The first stage employees the capacitive feedback with the source degenerated inductive feedback to achieve input wideband matching, the second stage adopts current-reused cascaded common-source structure to lower the power consumption. To obtain flat gain over a wide bandwidth, the shunt-series peaking inductor is used Besides, the output impedance matching was achieved with the series L-C network. To demonstrate the feasibility of the LNA, a 3.1 ~ 10.6 GHz LNA was designed and fabricated using the TSMC standard 0.18μm 1P6M CMOS process. The measurement results of the UWB LNA have flat gain of 6.66 dB, input return loss smaller than -10.7dB,output return loss small than -10.07 dB, good isolation of -28.25 dB, superior noise figure of 3.13~7.05 dB, P1dB of -16 dBm, IIP3 of -10dBm with the power consumption of 26.7 mW under the 1.5 supply.