| Title: | SIMULATABLE TIMING MODEL FOR MOS LOGIC-CIRCUIT |
| Authors: | JOU, SJ SHEN, WZ JEN, CW LEE, CL 交大名義發表 電控工程研究所 National Chiao Tung University Institute of Electrical and Control Engineering |
| Issue Date: | 1-Dec-1987 |
| URI: | http://hdl.handle.net/11536/4596 |
| ISSN: | 0956-3768 |
| Journal: | IEE PROCEEDINGS-G CIRCUITS DEVICES AND SYSTEMS |
| Volume: | 134 |
| Issue: | 6 |
| Begin Page: | 276 |
| End Page: | 283 |
| Appears in Collections: | Articles |
- EMOTA - AN EVENT-DRIVEN MOS TIMING SIMULATOR FOR VLSI CIRCUITS / SHEN, WZ;JOU, SJ;TAO, YS
- CMOS NONTHRESHOLD LOGIC (NTL) AND CASCODE NONTHRESHOLD LOGIC (CNTL) FOR HIGH-SPEED APPLICATIONS / WANG, JS;WU, CY;TSAI, MK
- A new true-single-phase-clocking BiCMOS dynamic pipelined logic family for high-speed, low-voltage pipelined system applications / Tseng, YK;Wu, CY
- EVENT-DRIVEN INCREMENTAL TIMING FAULT SIMULATOR / JOU, SJ;CHIOU, SH;TAO, YS;SHEN, WZ
- 奈米互補式金氧半製程下之低漏電源箝制靜電放電防護電路 / 邱柏硯;Po-Yen Chiu;柯明道;Ming-Dou Ker
- LATCHED CMOS DIFFERENTIAL LOGIC (LCDL) FOR COMPLEX HIGH-SPEED VLSI / WU, CY;CHENG, KH
Loading...