| Title: | A SIMPLIFIED COMPUTER-ANALYSIS FOR NORMAL-WELL GUARD RING EFFICIENCY IN CMOS CIRCUITS |
| Authors: | CHEN, MJ WU, CY 交大名義發表 工學院 National Chiao Tung University College of Engineering |
| Issue Date: | 1-Aug-1987 |
| URI: | http://hdl.handle.net/11536/4626 |
| ISSN: | 0038-1101 |
| Journal: | SOLID-STATE ELECTRONICS |
| Volume: | 30 |
| Issue: | 8 |
| Begin Page: | 879 |
| End Page: | 882 |
| Appears in Collections: | Articles |
- Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology / Ker, MD;Lo, WY
- DESIGN-MODEL AND GUIDELINE FOR N-WELL GUARD RING IN EPITAXIAL CMOS / HUANG, CY;CHEN, MJ
- ANALYTICAL DESIGN FORMULATION FOR MINORITY-CARRIER WELL-TYPE GUARD RINGS IN CMOS CIRCUITS / CHEN, MJ;HUANG, CY;TSENG, PN
- 針對Giga-Hertz基底雜訊抑制的主動保護電路 / 王建龍;李育民;溫瓌岸
- Low-temperature characteristics of well-type guard rings in epitaxial CMOS / Huang, CY;Chen, MJ;Jeng, JK;Wu, CY
- Active Guard Ring to Improve Latch-Up Immunity / Tsai, Hui-Wen;Ker, Ming-Dou
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