低功率和寬注入鎖定範圍之除頻器

Abstract

本論文中，我們提出新穎又簡單的寬鎖定範圍除頻器。一般是採用峰值電感技術即增加電感數量，來增加鎖定頻寬的方法，而我們的電路不需要額外增加電感來達到加寬鎖定範圍的目的。本電路的設計架構是根據基本架構改良，我們以中心抽頭電感來取代傳統架構中的對稱電感，並額外加入一個電晶體在注入端電晶體與中心抽頭電感之間。這個架構加寬的鎖定範圍，由於它有兩種功能：(1)可以產生額外的注入電流，並由中心抽頭處流入，提升注入效率；(2)額外添加的電晶體與中心抽頭電感形成帶通濾波器，抑制非二次諧波的頻率成分。 本晶片是由TSMC 0.18μm CMOS 1P6M實現，面積為0.600×0.602 mm^2。在未注入訊號下，本晶片操作電壓源為1.2V時的功率消耗為1.58mW，自振頻率為4.72GHz；在訊號強度0dBm的訊號注入下，本晶片在鎖定狀態下的頻寬為9.2-10.6GHz，並且輸出功率在-4dBm以上。

In this thesis, we propose a new and simple current–reused direct injection-locked frequency divider (DILFD) with wide locking range property. Instead of using a common method, inductive peaking, which requires adding inductors to widen the locking range, the proposed circuit achieves the goal without adding inductor. The proposed current-reused DILFD is based on a conventional one but replaces the symmetric spiral inductor by a center-tap inductor, besides, we add an additional NMOS between the input NMOS and the center-tap inductor. This topology widens the locking range because that (1) an extra current feed at the center-tap of the inductor raises injection efficiency and (2) the additional NMOS and the center-tap inductor form a band-pass filter which suppress non-2rd-harmonics. The proposed ILFD is fabricated in TSMC 0.18μm CMOS 1P6M technology and the whole chip area is 0.600×0.602 mm^2. Under a free running condition, the power consumption is only 1.58 mW for the FD, from the 1.2 V supply and its oscillation frequency is 4.72 GHz. At the input power level of 0 dBm, the FD has a locking range of 9.2–10.6 GHz and its output power is above -4dBm.