| Title: | A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURES |
| Authors: | CHEN, MJ WU, CY 交大名義發表 工學院 National Chiao Tung University College of Engineering |
| Issue Date: | 1-Apr-1986 |
| URI: | http://hdl.handle.net/11536/4757 |
| ISSN: | 0018-9383 |
| Journal: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
| Volume: | 33 |
| Issue: | 4 |
| Begin Page: | 489 |
| End Page: | 493 |
| Appears in Collections: | Articles |
Files in This Item:
If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.
- A NEW APPROACH TO MODEL CMOS LATCHUP / WU, CY;YANG, YH;CHANG, C;CHANG, CC
- A NEW CRITERION FOR TRANSIENT LATCHUP ANALYSIS IN BULK CMOS / YANG, YH;WU, CY
- 深次微米CMOS時間介電崩潰及鎖定之研究 / 陳志輝;Chen, Zhi-Hui;陳明哲;Chen, Ming-Zhe
- Active Guard Ring to Improve Latch-Up Immunity / Tsai, Hui-Wen;Ker, Ming-Dou
- A NEW STRUCTURE-ORIENTED MODEL FOR WELL RESISTANCE IN CMOS LATCHUP STRUCTURES / CHEN, MJ;SZE, SC;CHEN, HH;WU, CY
- Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product / Lin, IC;Huang, CY;Chao, CJ;Ker, MD
- MODELING THE POSITIVE-FEEDBACK REGENERATIVE PROCESS OF CMOS LATCHUP BY A POSITIVE TRANSIENT POLE METHOD .1. THEORETICAL DERIVATION / KER, MD;WU, CY
Loading...