| Title: | AN EFFICIENT TWO-DIMENSIONAL MODEL FOR CMOS LATCHUP ANALYSIS |
| Authors: | CHEN, MJ WU, CY 交大名義發表 工學院 National Chiao Tung University College of Engineering |
| Issue Date: | 1-Apr-1986 |
| URI: | http://hdl.handle.net/11536/4760 |
| ISSN: | 0038-1101 |
| Journal: | SOLID-STATE ELECTRONICS |
| Volume: | 29 |
| Issue: | 4 |
| Begin Page: | 395 |
| End Page: | 407 |
| Appears in Collections: | Articles |
- Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology / Ker, MD;Lo, WY
- Anomalous latchup failure induced by on-chip ESD protection circuit in a high-voltage CMOS IC product / Lin, IC;Huang, CY;Chao, CJ;Ker, MD
- Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs / Hsu, Sheng-Fu;Ker, Ming-Dou
- A NEW ANALYTICAL 3-DIMENSIONAL MODEL FOR SUBSTRATE RESISTANCE IN CMOS LATCHUP STRUCTURES / CHEN, MJ;WU, CY
- 次微米互補式金氧半鎖定及基座偏壓產生器 / 周業輝;Yeh-Huei Jou;陳明哲;Ming-Jer Chen
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