| Title: | AN EFFICIENT TIMING MODEL FOR CMOS COMBINATIONAL LOGIC GATES |
| Authors: | WU, CY HWANG, JS CHANG, C CHANG, CC 電控工程研究所 Institute of Electrical and Control Engineering |
| Issue Date: | 1985 |
| URI: | http://hdl.handle.net/11536/4823 |
| ISSN: | 0278-0070 |
| Journal: | IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS |
| Volume: | 4 |
| Issue: | 4 |
| Begin Page: | 636 |
| End Page: | 650 |
| Appears in Collections: | Articles |
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- 自動化電晶體尺度設計之電腦輔助設計程式 / 黃振昇;HUANG, ZHEN-SHENG;吳重雨;WU, CHONG-YU
- NEW FAST FIXED-DELAY SIZING ALGORITHM FOR HIGH-PERFORMANCE CMOS COMBINATIONAL LOGIC-CIRCUITS AND ITS APPLICATIONS / HWANG, JS;WU, CY
- CMOS NONTHRESHOLD LOGIC (NTL) AND CASCODE NONTHRESHOLD LOGIC (CNTL) FOR HIGH-SPEED APPLICATIONS / WANG, JS;WU, CY;TSAI, MK
- ANALYSIS AND DESIGN OF A NEW RACE-FREE 4-PHASE CMOS LOGIC / WU, CY;CHENG, KH;WANG, JS
- EFFICIENT TECHNIQUES IN THE SIZING AND CONSTRAINED OPTIMIZATION OF CMOS COMBINATIONAL LOGIC-CIRCUITS / HWANG, JS;WU, CY
- EFFICIENT PHYSICAL TIMING MODELS FOR CMOS AND-OR-INVERTER AND OR-AND-INVERTER GATES AND THEIR APPLICATIONS / WU, CY;SHIAU, MC
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