| Title: | A NEW APPROACH TO MODEL CMOS LATCHUP |
| Authors: | WU, CY YANG, YH CHANG, C CHANG, CC 工學院 College of Engineering |
| Issue Date: | 1985 |
| URI: | http://hdl.handle.net/11536/4824 |
| ISSN: | 0018-9383 |
| Journal: | IEEE TRANSACTIONS ON ELECTRON DEVICES |
| Volume: | 32 |
| Issue: | 9 |
| Begin Page: | 1642 |
| End Page: | 1653 |
| Appears in Collections: | Articles |
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- Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology / Ker, MD;Lo, WY
- TRANSIENT ANALYSIS OF SUBMICRON CMOS LATCHUP WITH A PHYSICAL CRITERION / KER, MD;WU, CY
- 深次微米CMOS時間介電崩潰及鎖定之研究 / 陳志輝;Chen, Zhi-Hui;陳明哲;Chen, Ming-Zhe
- Dependence of device structures on latchup immunity in a high-voltage 40-V CMOS process with drain-extended MOSFETs / Hsu, Sheng-Fu;Ker, Ming-Dou
- 一種存在於互補式超大型積體電路的雙橫向鎖住行為之探討 / 黃恆盛;Heng-Sheng Huang;張俊彥;C. Y. Chang
- 互補式金氧半暫態鎖住效應及晶片上靜電放電保護電路之研究. / 柯明道;Ming-Dou Ker;吳重雨;Chung-Yu Wu
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