使用於佈局相依效應之佈局萃取器實現

Abstract

隨著CMOS製程的持續演進，電晶體的閘極長度與閘極寬度已達到數十奈米等級，在相同的單位面積可容納更多的電晶體個數，製程技術的開發使得現行資訊產品的功能越來越強大。許多先進製程技術讓電晶體的電性表現更為出色，但這也讓設計端隨之產生新的挑戰。尤其是奈米等級的製程，不管是在元件模型的建立與萃取、設計工具的流程等等，都必須因應這些更為複雜的元件特性與相依效應而改變。

本論文討論各種佈局相依效應，並且完成了一個可萃取各種佈局相依效應之佈局萃取器，使得電路設計者在初期階段就可以進行快速的佈局萃取，進而了解電路受到這些相依效應的影響程度並即時修改電路，原本需要到驗證階段才能得知的相依效應影響在設計階段就可得知，加快了設計往返時間。本篇論文亦使用了一個 28nm 製程的類比電路進行此萃取器之驗證，並得到小於百分之一的pre-layout 與 post-layout simulation 誤差。

As CMOS process continuous scaling, both transistor’s gate width and gate length are on a scale of nano-meters. Thanks to the new process technologies, a single chip carries enormous amount of transistors. Those technological advances enable higher sophisticated system in the foreseeable future. On the other hand, they also lead to many layout proximity effects. The effects impact not only on transistor’s electrical characteristics, but also in device modeling, model extraction and circuit design flows.

In this thesis, we discussed different types of layout proximity effect and also realized a layout context extractor. The extractor detected the transistor’s placement context and reported it back to the design circuit. It shortens design cycle and minimize the uncertainty gap between pre-layout and post-layout simulations. The extractor was validated by a 28nm analog design circuit with BSIM4.6 model and achieved less than 1% difference between pre-layout and post-layout simulations.