| Title: | 應用於高速排序之移位暫存器陣列架構 Shift regsister array architectures for high-speed data sorting |
| Authors: | 蔡哲民 李鎮宜 電子研究所 |
| Issue Date: | 1984 |
| URI: | http://140.113.39.130/cdrfb3/record/nctu/#NT732428014 http://hdl.handle.net/11536/52033 |
| Appears in Collections: | Thesis |
- 應用於高速排序之移位暫存器陣列 / 蔡哲民;Jer-Min Tsai;李鎮宜;Chen-Yi Lee
- A shift register architecture for high-speed data sorting / Lee, CY;Tsai, JM
- HIGH-SPEED MEDIAN FILTER DESIGNS USING SHIFTABLE CONTENT-ADDRESSABLE MEMORY / LEE, CY;HSIEH, PW;TSAI, JM
- VLSI IMPLEMENTATION OF AN M-ARRAY IMAGE FILTER BASED ON SHIFT REGISTER ARRAY / LEE, CY;TSAI, JM;HSU, SC
- AN AREA-EFFICIENT MEDIAN FILTERING IC FOR IMAGE VIDEO APPLICATIONS / HSIEH, PW;TSAI, JM;LEE, CY
- A Two-Directional BigData Sorting Architecture on FPGAs / Lai, Bo-Cheng;Chen, Chun-Yen;Hsin, Yi-Da;Lin, Bo-Yen
- 應用於次世代定序之高速資料處理器設計與實現 / 吳易忠;楊家驤;Wu, Yi-Chung;Yang, Chia-Hsiang
- Novel architecture for ATM QoS management / Tsai, JM;Lee, CY
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