混合式資料驅動架構設計與在傳算器上製作其仿擬器

Abstract

在傳統的von Neumann架構，因為程式之執行受限於程式計數器（ program counter）之循序性，犧牲 了程式平行計算之可能性，而資料流 （dataflow）架構正提供一可能的解法。理論上，資料流架構可獲致程式 平行度之最大利用率。然而在動態（dynamic）資料流架構中，需要一配 對單元（matchingunit），負責運算元之配對 ，藉以控制指令之執行。 一般而言，配對單元是資料流架構的主要瓶頸。因此如何改進配對處理（ matchingprocess）之效率是設 計資料流架構的主要課題之一。本論文提 出一結合資料流與傳統式管線（pipeline）架構之 混合式架構。此架構 由傳統式的管線構成，但其程式之執行採用資料流驅動方式，所以不需要 程式計數器。而運算元之配對方式也和動態資料流架構不同，運算元並非 置於配對單元等待，而是儲存在記憶體中，以其位址作為此運算元之標籤 ，且此位址是由編譯器決定的。因此運算元的配對可經由存取記憶體動作 完成。此外為仔細評估此架構之可行性，而製作一在傳算器（transputer ）上執行之仿擬器（emulator）。 In von Neumann architecture, the sequential behavior of program counter limits the parallelism of execution. Dataflow execution model provided an efficient alternative. At the abstract level (not necessarily the implementation) it provides the possibility of exploiting maximal parallelism in a program. However, dataflow execution model possesses some intrinsic problems on its own. In a dynamic data-driven structure, a matching unit is required to collect all data with the same tag. In general, matching unit is the major bottleneck of the dynamic dataflow architecture. Thus, how to improve the performance of matching process is one of the major course in designing a dataflow computer. In this thesis, we presented a hybrid computer architecture which incorporated dataflow computation into the von Neumann style pipelined computer. The proposed architecture consists of a pipeline, and the execution of instructions is data-driven. Furthermore, data, instead of being flown around, are stored in memory and the direct memory addresses of the data are used as the tags associated with them and no extra hardware units or matching operations are required in our architecture. Also, an emulator is designed on Transputer to evaluate the proposed architecture.