符合數位儲存系統D-3規格之錯誤訂正碼解碼器之超大型積體電路設計

Abstract

新一代的數位視訊產品,錯誤訂正碼系統是使其擁有高品質的主要貢獻者. 在本論文中,我們遵照最新制定的電視數位資料儲存標準D-3規格完成一個 新的高速錯誤訂正碼解碼系統.在其中的內碼部份,我們提出了一套含四個 步驟的新型管線式架構來解(95,87)RS縮短碼.在外碼部份,我們則採用了 另一套僅含兩個步驟的新型管線式架構來解(136,128)RS縮短碼.這兩套新 型的架構所使用的時鐘脈波週期,長度皆可明顯地縮短.使用0.8微米技術, 我們完成了兩組分別適用於內碼及外碼的錯誤解碼系統.內碼解碼系統的 晶片面積為4.9mm x 4.9mm,包含約九萬個電晶體 .外碼解碼系統的晶片面 積則為4.9mm x 4mm,包含約六萬五千個電晶體.兩組晶片皆使用一個外接 的重設控制信號及一個單相的時鐘脈波.最後用軟體所模擬的資料處理速 度每秒超過兩百萬位元,遠超過D-3規格所要求的速度. The error-correcting-codes(ECC) system contributes largely to the quality improvement in the new generation of video products. A high speed ECC system is implemented following the D-3 format for the television digital recording. In the inner code, a modified four-stage pipelined algorithm is proposed to decode the (95,87) shortened RS code. In the outer code, we adopted an extended two-stage pipelined algorithm to decode the (136,128) shortened RS code. Both algorithms can evidently shorten the system clock comparing to the traditional structures. Using the proposed algorithms, two decoder chips for the inner and outer code are implemented. The area of the inner code decoder chip is 4.9mm by 4.9mm, with about 90000 transistors. The area of the outer code decoder chip is 4.9mm by 4mm, with about 65000 transistors. One external reset control signal and one single phase clock are used for both chips. The simulated data rate by IRSIM is over 200 Mbps and is over the requirement of D-3 format (63.3Mbps).