使用切換型比較器完成之快閃式互補金氧半類比數位轉換器的設計與分析

Abstract

本論文描述我們設計完成之快閃式類比數位轉換器,此類比數位轉換器係 依標準之DPDM CMOS 0.8微米製程技術來設計,且經過HSPICE模擬驗証符合 八位元解析度與每秒50百萬次取樣的要求,最後我們並將此類比數位轉換 器完整地製成晶片面積為1740乘1280微米平方的單一積體電路。對快閃式 類比/數位轉換器而言,其工作速度及功率消耗取決於內部比較器的速度與 功率,雖然切換比較器相對於較複雜的差動式比較器而言稱的上是一種天 生省電型的比較器,但我們仍須盡力加大其訊號對雜訊比以克服其易受雜 訊干擾的缺點。正如預期一般,此一工作可經由決定出反相放大器,自動歸 零電路,取樣開關等之內部電晶體及交流訊號藕合電路的理想尺寸完成。 This thesis describes a Flash A/D converter we have designed. The A/D converter is designed with the 0.8-um DPDM CMOS process technology and has been verified by the HSPICE simulator under the requirements of eight-bit resolution and 50 million samples per second. Finally, this flash A/D converter has been completely implemented in a single chip with active area of 1740um x 1280um. For a flash A/D converter, its operating speed and power consump- -tion are determined by that of the comparator in it. Although the chopper-type comparator with its simple circuit structure is an inherent low power amplifier relative to the complicate differential type, we still need to be engaged in maximizing the signal-to-noise ratio to overcome its drawback of poor noise immunity. As expected, such a task can be achieved by optimizing the capacitance of the AC signal coupling capacitor and the transistor size of the inverting amplifier, the autozero, and the sampling switches.