一個使用在詗速網際網路上的交叉開闢平行路徑器架構

Abstract

在網際網路（Internetworking）中大部份都是利用路徑器（Router）來連接多個區域網路（LAN），使區域網路之間能夠互相傳遞資訊。由於光纖（Optical Fiber）普遍的使用在資料通訊網路中，因此在FDDI (Fiber Distrbuted Data Interface)100 Mbps速度的要求下，目前以單一處理機（Single-Processor）為架構的路徑器已經不能滿足使用者的需求，它的能力成為整個系統的瓶頸。為了滿足FDDI在速度上的要求，必須改進舊有的路徑器。在多種改進方案之中，以具有多處理能力（Multiprocessing）的平行路徑器（Parallet Router），是比較可行的方法。過去已經有多篇文章在探討平行路徑器的設計，其中在1993年由IBM公司的研究部門所提出的架構就可達200 Mbps的效率。雖然已經可以滿足基本的需求，但面對未來速度接近1 Gbps的非同步傳輸模式（Asynchronous Transmission Mode）交換網路時，仍然顯得相當不足。 本篇論文提出一個新的平行路徑器架構，採用交叉開關機制（Corssbar Switch Mechanism）來取代原有架構中的高速匯流排（High Speed Bus）架構。因為交叉開關機制具有平行傳輸與低傳輸延遲的優點，因此可改進原有架構中匯流排成為傳輸瓶頸的缺點，所以在整體系統的效益上會有相當程度的提昇。另外本篇論文也提出一個新的重排序演算法，這個演算法能在交叉開關平行路徑器上運作，達到封包在傳送過程中前後順序一致的目標。透過理論上的數據推算與實際模擬的結果，新的架構具有接近1 Gbps的效率。當封包（packet）大小在64, 128和256 bytes時，系統的效率會隨處理器個數的增加而成線性關係的成長。這個現象指出了，系統的效率是以處理器的個數來決定的。然而在封包大小為512和1024 bytes時，系統的效率會受限於交叉開關的傳輸埠（Port）數量和封包的碰撞機率（Contentious Proability）。

One of the most powerful ideas in data communications to date has been the notion of internetworking. The use of routers makes internetworking possible. At the Fiber Distributed Data Interface (FDDI) speeds, the computing power of the parallel router becomes the performance bottleneck. The introduciton of the existing single-processor router has shown that throughput of up to 200 Mbps can be achieved. However, at the advent of the gigabit networking, today's parallel routers are not able to satisfy the performance requirement of the future Asynchronous Transmission Mode (ATM) switching network. The parallelism of existing paralled routers is realized by a set of processors (multiprocessor) interconnected via a high speed bus. Unfortunately, this type of a rchitecture renders the bus instead of the processor to be the system bottleneck. In this paper, we propose a parallel router architecture which employs the crossbar swiching concept. Due to the inherited nature of minimum transmission delay of the crossbar switching system, this new architecture can significantly improve the performance of the existing parallel router. A resequencing algotithm is developed to make sure packets, which are transmitted through the crossbar switch, can be received in the correct order at the receiving end. According to both analytical and simulation results, this new architecture can support a traffic load which is close to 1 Gbps. For packet siaes 64, 128 and 256, the throughput increases linearly as the number of processors increasis. This phenomenon indicates that the number of processors determines the system performance. For packet sizes 512 and 1024, the system bottleneck is moved from the processor to the crossbar swhich, du to the limited number of ports inside the switch and the contentious probability among packets.