互補式金氧半導體╱在絕緣體上矽晶元件模擬：聚集模式與加強模式之比較

Abstract

由於半導體元件尺吋的日益縮小，更快的速度、更小的漏電及更高的電路 密度乃是積體電路技術追求的目標。當元件尺吋縮小至 0.25微米時,由於 元件隔絕容易、短通道效應降低、Latch-up效應消失．．．等特點，使得 在絕緣體上矽晶用來製作互補式金氧半導體元件在超大型積體電路上的應 用遠優於傳統之基材元件。除此之外，完全匱乏在絕緣體上矽晶元件更具 有低漏電及高飽和電流的優點，在低功率消耗電路及快速元件的應用上更 具重要性。在絕緣體上矽晶元件中，影響最大為閘極氧化層厚度、矽晶厚 度及通道doping濃度。這些參數直接影響到在絕緣體上矽晶元件關閉狀態 的漏電流和飽和電流推動能力，也因而影響到電路的功率消耗及漏電大小 。此外，完全匱乏Accumulation模式元件更具備優越的特性，不過，它也 有必須克服的問題。本計劃藉由二圍模擬方法研究各種參數對完全潰乏在 絕緣體上矽晶元件之門檻電壓、次門檻斜率及電流推動能力之影響，用以 找出最佳的元件操作，同時探討元件運作之機制。 Silicon on insulator (SOI) technology is a promising candidate for future ULSI as the quality of SOI material continues to improve. Thin (less than 1000A) SOI film thickness which makes fully depleted SOI MOSFETs is important for minimization of short channel effects, easy isolation, elimination of latch-up, steeper subthreshold slopes, and increased current drive capability which will make low power and high speed devices work well. The purpose of this research is to investigate: A. the dependence of fully depleted SOI as the devices are scaled down to deep submicron area. Three key parameters: (1). The threshold voltage (2). Subthreshold swing (3). Current drive capability B. the scaling rule of CMOS/SOI. Si film thickness, gate oxide thickness , channel length, and channel doping will be the key parameters in this investigation. 2D device simulator is used in device optimization and in gaining insight of physical mechanism.