用於數位行動通訊系統下之頻率漂移補償器電路設計

Abstract

在數位行動通訊系統中，因為車輛移動所造成之都卜勒效應與載波頻率和 本地振盪器頻率之差，使得接收信號的頻率產生漂移。在差分檢測法中， 它會使基頻訊號產生一固定之相位旋轉，因而檢測後所得到之錯誤比次率 效能變差。因此我們必須在差分檢測系統中加入一個頻率漂移補償器電路 來改進性能。在本論文中，我們針對基頻回授頻率漂移補償技術進行設計 與評估。在北美數位行動通訊標準中，同步序列只有14個，因此頻率漂移 補償器在收斂上必須快速且穩定。在電腦模擬中，我們考慮在不同的訊號 雜訊比、以及不同車速下來做評估分析，我們發現收斂速度以及補償效果 都相當不錯。依據此結果來設計且簡化電路，並撰寫 Verilog語言來描述 電路，經驗證無誤。 In the digital cellular mobile communication, the Doppler effect owing to vehicle movement and the mistuning of local oscillator for carrier frequency will result in the frequency drift in the receiver signal. In the differential detection, this will lead to a constant frequency rotation in the baseband signal. Therefore, BER performance will severely degrade by the frequency offset. Thus, frequency offset compensator is required to improve the performance. In this thesis, we adopt a baseband feedback Frequency-Drift -Compensation (FDC) scheme as basis of design. In the ADC IS-54 standard, the preamble length of the is only 14 symbols. Therefore, the frequency offset compensator has to be quick in convergence rate and stable. In our computer simulation, we develop a program with C++ language to simulate the system under different SNR, and vehicle speeds. The performance in the convergence rate and BER can achieve the requirement. A VLSI design is also completed and verified successfully with a gate level circuit simulation.