以神經元雙載子電晶體實現之新型細胞元化類神經網路

Abstract

本論文提出以0.6μm single-poly-triple-metal n-well互補式金氧半技術設計並製造的新型細胞元化類神經網路。為簡化傳統細胞元化類神經網路的神經元電路，我們將由互補式金氧半導體製程中的寄生雙載子電晶體和雜散電阻所形成的神經元雙載子電晶體元件架構應用在細胞元化類神經網路的積體電路實現上，提出兩種細胞元的電路。其一是以神經元雙載子電晶體實現細胞元中的神經元和加權值，其二是以神經元雙載子電晶體實現細胞元的電流輸入端和加權值，並提出以二極體實現神經元的電路架構。 在這兩種細胞元的電路中，細胞元的加權值是由神經元雙載子電晶體中的電阻值決定，所以以由金氧半電晶體實現的可調式金氧半電阻取代雜散電阻，即可使細胞元化類神經網路具有調整加權值的能力。 相較於傳統細胞元化類神經網路的硬體實現，利用神經元雙載子電晶體或二極體的架構實現神經元，不僅簡化電路的複雜度，還可以使電路的佈局更緊密。以可調式金氧半電阻實現加權值，一方面也簡化傳統加權值的電路，提高細胞元的密度，另一方面使加權值的調整變得很容易，由控制金氧半電晶體的閘極電壓即可調整加權值。 兩種細胞元電路所構成的細胞元化類神經網路均已由HSPICE模擬驗證，第一種電路可以達到雜訊消除的功能，第二種電路則可以應用在雜訊消除和陰影偵測上。其中第二種電路以0.6μm single-poly-triple-metal n-well互補式金氧半技術設計與製造。晶片中包含可以實現雜訊消除的16×16陣列和可以實現陰影偵測的1×5陣列，每個細胞元的佈局面積是80×89μm2。兩個陣列的加權值均可調，因此經由加權值的調整，即可達成雜訊消除或陰影偵測的功能。晶片的量測結果亦驗證所提出的細胞元化類神經網路架構可以達到上述兩種功能。

In this thesis, new structures of cellular neural networks designed and fabricated in 0.6μm single-poly-triple-metal (SPTM) n-well CMOS process are presented. The device structure called the neuron-bipolar junction transistor (nBJT) consists of the parasitic PNP bipolar junction transistor and the spreading base resistor array in the CMOS process. To simplify the circuit of the neuron in cellular neural networks, the nBJT is used in the integrated circuit implementation of cellular neural networks, and two circuit designs of the cell are proposed. In the first design, the nBJT is used to implement the neuron and weights of the cell. In the second design, it is used to implement the current summation and weights of the cell, and a diode structure is proposed to realize the neuron. In the two circuit designs of the cell, weights of the cell are realized by the resistance of the resistors in nBJTs. Thus if the spreading resistors are replaced by tunable MOS resistors, the programmable capability is achieved. Compared with previous hardware implementations of cellular neural networks, using the nBJT or the diode structure to realize the neuron not only simplifies the complexity of the circuit, but also makes the layout more compact. Realizing weights by tunable MOS resistors is also a simpler way than previous. Thus high packing density can be achieved. Moreover, weights can be easily tuned by controlling the gate voltages of the MOSs. The functions of the cellular neural networks constructed by the proposed two circuit designs of the cell have been verified by HSPICE simulations, respectively. The first circuit can perform noise removal and the second can be applied in noise removal and shadow detection. The second kind of complete circuits are designed and fabricated in 0.6μm single-poly-triple-metal (SPTM) n-well CMOS process. The chip contains a 16×16 array for noise removal and a 1×5 array for shadow detection. The layout size of each cell is 80×89μm2. Weights of both arrays are programmable, and thus both noise removal and shadow detection can be performed by tuning the weights. Measurement results on the chip also verify that the proposed structure of cellular neural networks can achieve the above two functions.