磊晶層厚度對MOS靜電放電可靠性之衝擊

Abstract

靜電放電保護隨著積體電路尺寸不斷的縮小而日趨重要。在日常生活中，兩個不同物體相互接觸時就會有靜電的累積。積體電路一旦接觸到其他物體時，累積的靜電就會轉移到積體電路上造成損毀。尤其，CMOS IC 的輸入極常連接到閘極氧化層，此閘極氧化層在深次微米製成技術中僅有50~70Å。如此薄的氧化層只要十伏特左右的靜電電壓便會打穿，而幾百伏特至幾千伏特的靜電電壓隨時發生在我們的周圍。因此，在積體電路中，必須要有適當的靜電放電保護設計。 本篇論文廣泛地探討0.30微米閘長的閘極接地n型金氧半場效電晶體的靜電放電保護電路。此種保護電路已廣泛地被應用在輸出與輸入極，並且經發現與磊晶層厚度相關。文中，我們引用相關參數的模型以觀察各參數在不同磊晶層的變化。最後，我們試著將所有模型連接起來，用以描述在靜電放電的過程中，n型金氧半場效電晶體的反應機制。

Electrostatic Discharge(ESD) protection has become more and more important as the device feature size scales down. In daily lives, the charging process occurs when two dissimilar materials rub together and then separate. Throughout the integrated circuit’s overall operation time, any contact with another object can result in a discharging process and catastrophic damage, especially for CMOS IC. In such circuits, the input/output pins are usually connected to internal gate oxide that is about 50~70Å thick in present submicron process technologies. A 10 V DC voltage can easily cause gate oxide wear-out. However, a 2 kV transient voltage or greater is generated when ESD occurs. Thus, an efficient ESD protection scheme is inevitably needed. This thesis extensively explores the ESD protection device in 0.30mm gate length nMOS transistor. The device is widely utilized in the input/output stages for ESD protection and its ESD capability is found to be related to epi-layer thicknesses. In this work, the existing substrate current model and avalanche generation model are cited to investigate parameter dependence on epi-layer thicknesses. Finally, we try to build up a high-current bipolar snapback I-V model to characterize the ESD protection mechanism of nMOS transistor. Abstract (English)…………………………………………………………ii Acknowledgement……………………………………………………………iii Contents...…………………………………………………………………iv Figure Captions...…………………………………………………………vi Chapter 1 Introduction……………………………………………………1 Chapter 2 Operation Theory of ESD Protection Devices……………3 2.1 ESD Protection Devices……………………………3 2.2 NMOS Transistor……………………………………4 Chapter 3 ESD Verification Methodology and Test Setup for Grounded-Gate NMOS Transistor………………………6 3.1 Sample Preparation…………………………………6 3.2 Grounded-Gate nMOS Transistor DC IV…………7 3.3 Current Pulsing I-V Measurement………………7 Chapter 4 Model Derivation and Parameter Extraction………………9 4.1 Model Derivation……………………………………9 4.1.1 Substrate Current Model………………………9 4.1.2 Avalanche Generation Model…………………9 4.1.3 Grounded-Gate nMOS Snapback I-V Model…11 4.2 Parameter Extraction Methodology……………12 4.2.1 Substrate Current Isub………………………12 4.2.2 Multiplication Factor M……………………12 4.2.3 Bipolar Current Gain…………………………13 4.2.4 Series Resistance……………………………15 Chapter 5 Epitaxial Layer Thickness Effects on ESD Design……17 Chapter 6 Conclusion………………………………………………………19 References……………………………………………………………………20 Vita