使用改進式電流驅動邏輯閂鎖器之百億位元/每秒資料與時脈回復電路

Abstract

隨著互補式金氧半製程技術的發展，以及處理器運算能力的快速提升，顯示著用以傳輸資訊的寬頻資料連結越來越顯得重要。在許多的應用中，比如說電腦內部、電腦與電腦間和電腦與週邊間的介面，這樣的連結通常是一個很重要的部分，也是目前整體系統操作速度的瓶頸。為了克服在資料傳輸過程中由各種雜訊源所導致的訊號完整性問題，接收器在整個高速連結效能的表現中扮演了一個重要的角色，而其中最複雜的部分就是資料與時脈回復電路的設計，傳統上，為了在能操作在高頻下，製程上大都採用GaAs METFET, GaAs HBT或Si BiCMOS 製程。然而，由於深次微米互補式金氧半製程本身高速、低成本、低功率、高度整合的優勢，深次微米互補式金氧半製程也已經被考慮使用在這些高速電路。 論文主題在於使用標準互補式金氧半製程實現一個使用我們改進過後的電流驅動閂鎖器10Gb/s資料與時脈回復電路。並比較其和傳統電流驅動閂鎖器對資料與時脈回復電路效能的改進。此資料與時脈回復電路採用了亞歷山大數位式相位比較器，對稱式互斥或閘和LC壓控振盪。電路採用台積電0.18um的製程技術，在1.8V的電源供應下消耗130毫瓦(包含輸出緩衝器)。使用改進過後的電流驅動閂鎖器電路的重新取樣資料抖動為7.5ps，比原本的電流驅動閂鎖器電路的資料抖動11.2ps來得佳。

The scaling of CMOS process technologies and the increasing computational capability of processors show that high bandwidth links to communicate information are getting more and more important. Such high speed links are necessary parts of many applications, such as inner computer, computer-to-computer, or computer-to-peripheral interfaces, and they are the bottleneck of the system operating speed. To overcome the signal integrity problems induced by various noise sources during data transmission, the receiver design plays a significant role in the overall performance of high speed links. The design of clock and data recovery circuits is the most complicated part of the transceiver implementation. Traditionally, such high-speed circuits used for multi-Gb/s data communication were implemented with either GaAs METFET, GaAs HBT, or Si BiCMOS technology. However, the deep sub-micron CMOS technology is now being considered in these high-speed circuits because of its high speed, low cost, low power dissipation, and highly integrated capability. The goal of this work is to use a standard CMOS process to implement a 10Gb/s clock and data recovery (CDR) circuit using the improved MCML latch. Comparison of the CDR performance between using improved MCML latch and using common MCML latch are provided. This clock and data recovery circuit uses an Alexander bang-bang phase detector, symmetry XOR gates and a LC tank Voltage-Controlled Oscillator (VCO). The circuit is designed in TSMC 0.18-um CMOS technology, consuming 130mW(including output buffers) from a 1.8V supply. The peak-to-peak jitter of the retimed data of CDR using the improved MCML latch is 7.5ps better than the 11.2ps peak-to-peak jitter of the retimed data of CDR using common MCML latch.