Title: 應用於3.1~10.6 GHz超寬頻射頻前端接收器
The Design of a 3.1 ~ 10.6 GHz CMOS Direct-Conversion Receiver Front-End for UWB Applications
Authors: 羅怡凱
Yi-Kai, Lo
吳重雨
Chung-Yu Wu
電子研究所
Keywords: 射頻積體電路;無線通訊;接收器;UWB;WLNA;RF IC;Wireless Communication;Receiver;超寬頻;寬頻低雜訊放大器
Issue Date: 2006
Abstract: 由於對低功率、高傳輸速率無線網路的需求日與劇增,傳統的無線網路規格IEEE 802.11 a/b/g 已經無法提供滿足此需求。本篇論文闡述一個應用於3.1~10.6 GHz之超寬頻射頻前端接收器的設計方法與製作技術並依據國際電子電機學會所制定的802.15.3a規格作設計。論文中提出一個新的寬頻低雜訊放大器和一個寬頻的載波產生器、一個正交降頻混波器以及輸出緩衝器作為量測考量。寬頻低雜訊放大器同時接收3.1~10.6 GHz的訊號而載波產生器提供了所需要的14個載波頻率給予降頻混波器完成對輸入訊號的降頻處理。 根據模擬及量測結果證實,由於寬頻載波產生器中的電壓控制震盪器的震盪頻率漂移影響,此接收器只能處理3.1~5.4 GHz的訊號。量測結果顯示此接收器在此一頻帶範圍內的雜訊指數為6.5~7 dB, 頻寬內增益為6.9~10.7 dB,輸入1dB增益壓縮點為-16~-17.8 dBm輸入端三諧交越點為-5~-2.5 dBm,頻帶外的輸入1dB增益壓縮點為-14~-18 dBm,由二階失真引起的頻帶外二階交越點為4~5.8 dBm。除了載波產生器的工作電壓為1.6-V外,其他電路操作在1.2-V的工作電壓下,總功率消耗為94 mW,晶片面積為3.7 mm2。 此外,本論文將會討論造成此接收器功能不完全,以及功率消耗遠多於模擬結果的原因,並提出解決與修正的方法重新模擬。最後,經由重新模擬以及修正電路後的結果,證實此接收器可實現一個低功率、高傳輸速率無線通訊系統。在未來研究中將會進行一完整的寬頻收發器的實現以及整合。
As the increasing demands for low-power and high data-rate wireless communication, conventional wireless local area network of IEEE 802.11 a/b/g has found it difficult to suffice these requirements. In this thesis, the design methodology and implementation of a 3.1~10.6 GHz direct-conversion receiver for UWB application are presented according to the recently published IEEE 802.15.3a specification. The proposed direct-conversion receiver are composed of a new wideband low-noise amplifier (WLNA) used to receive 3.1~10.6 GHz signal simultaneously and a carrier generator to generate required 14-band carriers, and I/Q down-conversion mixers with output buffers for correct down-conversion of input signals and measurement consideration. Based on the simulation and measurement results, the proposed receiver receives signals of 3.1~5.4 GHz as a result of the oscillating frequency drift of VCO in the carrier generator. The measurement results present a overall noise figure (NF) of around 6.5~7dB, gain of 6.9~10.7 dB, input-referred 1-dB compression point (P1dB)of -16~-17.8 dBm, input third-order intercept point (IIP3) of -5~-2.5 dBm, out-of-band P1dB of -14~-18 dBm, and out-of-band IIP2 from second-order modulation of 4~5.8 dBm. It consumes 94 mW under 1.2-V power supply for WLNA and down-conversion mixers and 1.6-V for the carrier generator. Besides, a discussion about the malfunction and reasons of extraordinary high power consumption of the receiver is made; furthermore, a modification and revised-simulation of the receiver are proposed and done for further verification. In the light of revised-simulation results, the proposed receiver is confirmed to be suitable for low-power and high data-rate wireless communication systems. Future research will be conducted to implement a thorough transceiver for UWB applications.
URI: http://140.113.39.130/cdrfb3/record/nctu/#GT009311602
http://hdl.handle.net/11536/78073
Appears in Collections:Thesis


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