應用於參考電壓電路設計之高迴變率AB類放大器

Abstract

大多數的類比電路，都需要參考用的電壓、電流、或是『時間』。參考電壓提供一個準則，如DAC或ADC的LBS大小、穩壓器（Regulator）的輸出電壓位準、電池充電的開和關等等，都是由參考電壓源或參考電流源所提供來決定。近年來，由於製程的進步，以及環保的需求，使得系統操作電壓不斷地下降，本論文提出幾種不同型式帶差參考電路（ bandgap voltage reference）來討論。

本論文主要內容是改善傳統帶差參考電路內部op的迴變率及頻寛，並且，依據傳統帶差參考電路的缺點來加以討論，就如供給電壓必須超過1V以上（1.6V~4V），我們則是利用另一種帶差參考電路來改善；使其供給電壓為（0.98V），但因為電路過於龐大，我們利用次臨界區（subthreshold region）操作的溫度補償電路來大大縮小面積，然而，由於還有電阻補償參考電壓，所以我們就採用真正全CMOS並能供給0.9V~4V的帶差參考電路，來一一作比較。

在本論文中實現了各個帶差參考電路的模擬結果，能夠真正完成操作在供應電壓1V以下，並縮小晶片所佔面積及使用TSMC 0.35um CMOS製程進行設計。

Most of analog circuits need reference voltage circuits for developing accurate signal process. Bandgap reference voltage can provide a reference standard for digital-to-analog (DAC) or analog-to-digital (ADC) converters. Besides, the designs of regulators also need the temperature independent reference voltage to provide a regulated and stable supply voltage to system-on-chip (SoC) systems. In the recent years, because of CMOS processing technology advance and eco-awareness, the system supply voltage is scaled down for low power and low voltage operation. The target of this thesis is to propose some useful designs of bandgap voltage reference for SoC systems.

The target of this paper to improve bandgap bowel of OP slew rate, bandwidth and amendment shortcomings, for example the minimum supply voltage needs to be greater than 1V（1.6V~4V）. In this thesis, the improvement is based on the previous literature with the minimized supply voltage about 0.98V. However, the circuit is too immense to be implemented in a small silicon area. Thus, we use the advantage of the subthreshold region for temperature compensated voltage reference generator to reduce the silicon area.

The advantage of the circuit is the simple design with only one resister for temperature compensated voltage by full CMOS technology. Besides, the supply voltage can be extended from 0.9V to 4V according to the design technique of the voltage reference generator compared to the other voltage reference circuits.

According to the simulation results, the proposed bandgap reference designs complete sub-1V COMOS bandgap voltage reference with small silicon area. The circuits proposed by this thesis is suitable to be fabricated by 0.35-um CMOS technology.