低功耗高密度六位元每秒十億次取樣之類比數位與數位類比轉換器

Abstract

本論文提出一組以台積電0.13um CMOS Mixed-Signal/RF 1P8M製程所設計的低功耗高密度每秒十億次取樣率、六位元解析度之類比數位及數位類比轉換器。其中類比數位轉換器是採用使用平均內插技巧的快閃式結構，數位類比轉換器是採用電流式的結構。在類比數位轉換器的設計中，我們運用平均與內插的技巧來減少放大器使用的數目以降低功率消耗，並增加電路的線性度，編碼電路採用CMOS直接編碼邏輯結構來降低功率消耗。在數位類比轉換電路的設計上，我們在解碼電路上採混合式解碼電路架構設計，用以簡化解碼電路所使用的電晶體數，達到低功耗與減少佈局面積的目的。輸出電流源採串疊式組態設計，用以增加數位類比轉換器的輸出阻抗。本論文所提出的六位元資料轉換器對可提供超頻寬通訊系統做基頻資料轉換使用，經實體晶片量測得本組資料轉換對串接後運作於1.2V的電源供給及1GS/s的取樣頻率下，SFDR可達37dBc，類比數位及數位類比轉換器的功率消耗分別為46.37mW及30.57mW。

This thesis presents a pair of low power,high density 6-bit 1GS/s analog-to-digital converter (ADC) and digital-to-analog converter (DAC). Both data converters are realized in tsmc 0.13um CMOS Mixed-Signal/RF 1P8M process. The ADC is a flash type ADC with averaging and interpolating techniques. Averaging and interpolating techniques can reduce the number of amplifiers used to reduce the power and enhance the linearity. We use a direct encoder to reduce the logic power in the ADC design. The DAC is realized with the current-steering architecture. For the DAC design, we use a hybrid decoder to reduce layout area and cascode output current sources to achieve a higher output impedance. The proposed data converter pair can provide 6-bit resolution and is for the implementation of the baseband data transceiver in ultra-wideband communication systems. Under a 1.2V supply and 1GS/s sampling rate, the measured results in the ADC cascading DAC mode show that the data converter pair can archive an SFDR of 37dBc. The ADC consumes 46.37mW and DAC consumes 30.57mW in this testing mode, respectively.