| Title: | 次50奈米Multiple-Gate SOI CMOS的特性分析與模式建立 Investigation and Modeling of Sub-50 nm Multiple-Gate SOI CMOS |
| Authors: | 蘇彬 Su Pin 交通大學電子工程系 |
| Issue Date: | 2006 |
| Gov't Doc #: | NSC95-2221-E009-327-MY2 |
| URI: | http://hdl.handle.net/11536/89840 https://www.grb.gov.tw/search/planDetail?id=1309698&docId=242040 |
| Appears in Collections: | Research Plans |
- 次50奈米Multiple-Gate SOI CMOS的特性分析與模式建立 / 蘇彬;Su Pin
- 次100奈米SOI CMOS的RF/Analog特性分析與模式建立(I) / 蘇彬;Su Pin
- Hot-carrier-induced degradation for partially depleted SOI 0.25-0.1 mu m CMOSFET with 2-nm thin gate oxide / Yeh, WK;Wang, WH;Fang, YK;Chen, MC;Yang, FL
- An assessment of single-electron effects in multiple-gate SOI MOSFETs with 1.6-nm gate oxide near room temperature / Lee, W;Su, P;Chen, HY;Chang, CY;Su, KW
- 次100奈米SOI CMOS的RF/Analog特性分析與模式建立(II) / 蘇彬;Su Pin
- On the prediction of geometry-dependent floating-body effect in SOI MOSFETs / Su, P;Lee, W
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