| Title: | 單晶片系統驗證之核心技術開發-子計畫四：單晶片系統設計流程之實體驗證(I) Physical Verification for SoC Design Flow(I) |
| Authors: | 江蕙如 Jiang Iris Hui-Ru 交通大學電子工程系 |
| Issue Date: | 2005 |
| Gov't Doc #: | NSC94-2220-E009-042 |
| URI: | http://hdl.handle.net/11536/90508 https://www.grb.gov.tw/search/planDetail?id=1147358&docId=220367 |
| Appears in Collections: | Research Plans |
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