針對晶片系統連接網路之驗證與自動合成之研究(I)

Title:	針對晶片系統連接網路之驗證與自動合成之研究(I) The Study on Interconnection Verification and Synthesis for SoC(I)
Authors:	周景揚 JOU JING-YANG 交通大學電子工程系
Issue Date:	2002
Gov't Doc #:	NSC91-2215-E009-074
URI:	http://hdl.handle.net/11536/92736 https://www.grb.gov.tw/search/planDetail?id=784510&docId=150799
Appears in Collections:	Research Plans

Files in This Item:

If it is a zip file, please download the file and unzip it, then open index.html in a browser to view the full text content.