| Title: | 對以智財單元為基系統晶片設計之驗證與測試技術開發研究---子計畫IV:以智財單元為基系統晶片設計之測試技術研究 Testing Technology Development for IP-Based SoC Design |
| Authors: | 李崇仁 交通大學電子工程系 |
| Keywords: | 系統晶片;晶片設計;測試技術;System-on-chip (SOC);Chip design;Test technique |
| Issue Date: | 2001 |
| Gov't Doc #: | NSC90-2215-E009-084 |
| URI: | http://hdl.handle.net/11536/93688 https://www.grb.gov.tw/search/planDetail?id=665767&docId=126390 |
| Appears in Collections: | Research Plans |
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