| Title: | 深次微米互補式金氧半製程技術下之混合電壓輸出入界面電路與靜電放電防護電路的設計 Design of Mixed-Voltage I/O Interface Circuits and On-Chip ESD Protection Circuits in Sub-Quarter-Micron CMOS IC's |
| Authors: | 柯明道 KER MING-DOU 國立交通大學電子工程學系 |
| Issue Date: | 2000 |
| Gov't Doc #: | NSC89-2215-E009-103 |
| URI: | http://hdl.handle.net/11536/93852 https://www.grb.gov.tw/search/planDetail?id=583886&docId=109706 |
| Appears in Collections: | Research Plans |
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- 高性能混合訊號式介面積體電路---子計畫II---射頻電路之靜電放電防護技術與高速高低壓界面電路之研發(II) / 柯明道;KER MING-DOU
- ESD protection design with on-chip ESD bus and high-voltage-tolerant ESD clamp circuit for mixed-voltage I/O buffers / Ker, Ming-Dou;Chang, Wei-Jen
- ESD protection design for mixed-voltage I/O circuit with substrate-triggered technique in sub-quarter-micron CMOS process / Ker, MD;Chuang, CH;Hsu, KC;Lo, WY
- ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness / Ker, MD;Hsu, HC;Peng, JJ
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