A novel poly-Si nanowire TFT for nonvolatile memory applications

Title:	A novel poly-Si nanowire TFT for nonvolatile memory applications
Authors:	Hsu, Hsin-Hwei Lin, Horng-Chih Huang, Jian-Fu Huang, Tiao-Yuan 電子工程學系及電子研究所 Department of Electronics Engineering and Institute of Electronics
Issue Date:	2008
Abstract:	A novel ploy-Si nanowire TFT-SONOS device configured with independent double-gate structure was fabricated and characterized. The electrical characteristics including programming and erasing properties were studied. Adding an adequate top-gate bias was found to improve the programming efficiency, resulting in larger memory window.
URI:	http://hdl.handle.net/11536/952
ISBN:	978-1-4244-1656-1
Journal:	MTTD 2007 TAIPEI: PROCEEDINGS OF 2007 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN, AND TESTING (MTD '07)
Begin Page:	55
End Page:	56
Appears in Collections:	Conferences Paper