| Title: | 線海型陣列超大型積體電路之合成設計(II) Synthesis of VLSI Sea-of-Wires Arrays (II) |
| Authors: | 陳英一 CHEN ING-YI 私立中原大學電子工程研究所 |
| Issue Date: | 1994 |
| Gov't Doc #: | NSC83-0404-E033-005 |
| URI: | http://hdl.handle.net/11536/97283 https://www.grb.gov.tw/search/planDetail?id=110994&docId=17770 |
| Appears in Collections: | Research Plans |
- Fully process-compatible layout design on bond pad to improve wire bond reliability in CMOS ICs / Ker, MD;Peng, JJ
- Modeling of interconnect capacitance, delay, and crosstalk in VLSI / Wong, SC;Lee, GY;Ma, DJ
- Communication Synthesis for Interconnect Minimization in Multicycle Communication Architecture / Huang, Ya-Shih;Hong, Yu-Ju;Huang, Juinn-Dar
- 針對用戶可規劃閘陣列的面積與速度最佳化暨分割之研究(II) / 沈文仁
- 以資料分析為導向之新型態電子設計自動化研究---子計畫一：採用資料分析法則之可重組態單電子電晶體陣列自動合成技術( II ) /
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