可變速率視訊編解碼器架構模擬

Title:	可變速率視訊編解碼器架構模擬 Variable-Bit-Rate Video Codec Design and Simulation
Authors:	杭學鳴 HANG HSUEH-MING 交通大學電子工程研究所
Issue Date:	1993
Gov't Doc #:	TL-82-7202
URI:	http://hdl.handle.net/11536/97645 https://www.grb.gov.tw/search/planDetail?id=26671&docId=3280
Appears in Collections:	Research Plans

APA	杭., & HANG H. (1993). 可變速率視訊編解碼器架構模擬. https://www.grb.gov.tw/search/planDetail?id=26671&docId=3280.
Bibtex	@article{1993, title={可變速率視訊編解碼器架構模擬}, author={杭學鳴 and HANG HSUEH-MING}, journal={https://www.grb.gov.tw/search/planDetail?id=26671&docId=3280}, year={1993}, url={https://ir.lib.nycu.edu.tw/handle/11536/97645}, }